PC Hardware —

I/O Addresses

The bus system establishes a connection between the CPU and expansion devices and provides a path for the flow of data. The computer needs a way to track and control which device is sending data and which device is receiving; without such a means-the bus system-there would be complete chaos. The first step to establishing orderly communication is to assign a unique I/O address to each device.

NOTE
Everything in a computer, whether hardware or software, requires a unique name and address for the CPU to be able to identify what is going on. Bus-mastering devices might seem to get around this requirement, but they have their own controllers that track local traffic and "talk" to the CPU as needed.

I/O addresses are patterns of 1s and 0s transmitted across the address bus by the CPU. The CPU must identify the device before any data is placed on the bus. The CPU uses two bus wires-the IOR (Input/Output Read) wire and the IOW (Input/Output Write) wire-to notify the devices that the address bus is not being used to specify an address in memory, but rather to read to or write from a particular device. The address bus has at least 20 wires. However, when the IOW or IOR wire has voltage, only the first 16 wires are monitored.

To allow communication directly between the CPU and a device, each device responds to unique patterns or code built into it. If the CPU needs to check the error status of a hard disk drive controller, for instance, it activates the IOW wire and puts the correct pattern of 1s and 0s onto the address bus. The controller then sends back a message describing its error status.

All I/O addresses define the range of patterns assigned to each device's command set. The device ignores all commands outside its range. All devices must have an I/O address, and no two devices can have overlapping ranges. Basic devices on the address list have preset I/O addresses that cannot be changed. Other devices must be assigned to the open addresses, and they must be configured at installation. The following table lists standard PC I/O port address assignments.

PC/XT Port Used By PC/XT Port Used By
000h-00Fh DMA chip 8237A 2F0h-2F7h Reserved
020h-021h PIC 8259A 2F8h-2FFh COM2
040h-043h PIT 8253 300h-31Fh Prototype adapter
060h-063h PPI 8255 320h-32Fh Hard disk controller
080h-083h DMA page register 378h-37Fh Parallel interface
0A0h-0AFh NMI mask register 380h-38Fh SDLC adapter
0C0h-0CFh Reserved 3A0h-3AFh Reserved
0E0h-0EFh Reserved 3B0h-3BFh Monochrome adapter/ parallel interface
100h-1FFh Unused 3C0h-3CFh EGA
200h-20Fh Game adapter 3D0h-3DFh CGA
210h-217h Extension unit 3E0h-3E7h Reserved
220h-24Fh Reserved 3F0h-3F7h Floppy disk controller
278h-27Fh Parallel printer 3F8h-3FFh COM1
AT Port Used By AT Port Used By
000h-00Fh First DMA chip 8237A 278h-27Fh Second Parallel interface
020h-021h First PIC 8259A 2B0h-2DFh EGA
040h-043h PIT 8253 2F8h-2FFh COM2
060h-063h Keyboard controller 8042 300h-31Fh Prototype adapter
070h-071h Real-time clock 320h-32Fh Available
080h-083h DMA page register 378h-37Fh First parallel interface
0A0h-0AFh Second PIC 8259A 380h-38Fh SDLC adapter
0C0h-0CFh Second DMA chip 8237A 3A0h-3AFh Reserved
0E0h-0EFh Reserved 3B0h-3BFh Monochrome adapter/parallel interface
0F0h-0FFh Reserved for coprocessor 80287 3c0h-3CFh EGA
100h-1FFh Available 3D0h-3DFh CGA
200h-20Fh Game adapter 3E0h-3E7h Reserved
210h-217h Reserved 3F0h-3F7h Floppy disk controller
220h-26Fh Available 3F8h-3FFh COM1

I/O addresses have several important characteristics to remember:

  • I/O addresses have 16 bits; they are displayed with a hexadecimal number.
  • By convention, the lead 0 is dropped (because all I/O addresses have it).
  • Hexadecimal I/O addresses must use capital letters; they are case sensitive.

Setting I/0 Addresses

As mentioned, each device in a computer must have an I/O address. If a device qualifies as a basic device, it will have a standard, preset I/O address. The default setting for the I/O address will work and no changes are required.

If a device is not a basic device, and does not conform to the PCI Plug and Play specification on a Plug and Play-compatible system, read the manual that came with it. The manual will explain how to set the I/O address and define the limits for that device. I/O addresses are set by changing jumpers, switches, or through use of software.

On Plug and Play systems, PCI cards are self-configuring, and usually no intervention is needed to set I/O addresses for those cards. It is possible for Plug and Play cards to conflict with older ISA cards, which don't recognize the Plug and Play devices. If you are confronted with this problem, refer to the cards and the motherboard manual for possible resolution.

Managing I/0 Addresses

Devices assigned overlapping I/O addresses usually do not respond to commands and stop functioning. In such a scenario, a modem will dial but not connect; a sound card will start to play but will stop; a mouse pointer will appear but the mouse will not move. I/O overlaps can sometimes cause the machine to lock up intermittently.

I/O overlaps never happen independently. They usually appear immediately after a new device is installed. The best way to prevent I/O address overlaps is to document all I/O addresses. There are many commercially available programs that will check the I/O addresses for every device on your computer. You can also use Microsoft Diagnostics (MSD), a program provided with MS-DOS.

NOTE
If you are running Windows 95 or Windows 98 or the Windows NT operating system, you can use the Device Manager or System Information to locate and resolve IRQ and address conflicts. (See Tutorial 16, "Windows 95 and Beyond," for more information on the Device Manager.)